IBM POWER6 microprocessor physical design and design methodology

model Transistor-level VIM parasitic netlist Schematic, netlist Complete layout IBM J. RES. & DEV. VOL. 51 NO. 6 NOVEMBER 2007 R. BERRIDGE ET AL. 687 technology-specific wire models into the schematic netlist. Among the more accurately placed models in netlist, downstream analysis tools were more effective. Circuit optimization The IBM EinsTuner circuit tuning tool improved timing slack or performance by equally weighting many of the critical paths simultaneously while attempting to push the entire slack into positive territory with the IBM total positive slack (TPS) mode. Additionally, IBM free area recovery (FAR) within the EinsTuner tool included the optimization of noncritical paths in which circuits were reduced in size without migrating into critical or designlimiting territory. Essentially, this mode optimized these circuits for area recovery but, most importantly, reduced gate width by reducing the overall circuit leakage or dc power content of the macro design. Table 1 Terms, abbreviations, and acronyms for Figure 2. Tool name Full name Description VHDL (Very high-speed integrated circuit [VHSIC] Hardware Description Language) Modeling language to describe logical functionality of a system PIP Placement by instance parameter Custom macro cell placer STEP Steiner estimated parasitics Steiner wire parasitic estimator IBM EinsTuner — Circuit tuning tool LAVA Leakage avoidance and analysis FET type switcher tool VIM Very-large-scale integration (VLSI) instance model — IBM EinsTLT Transistor-level timer Transistor-level timing tool IBMmlsa IBM macro-level signal analysis Transistor-level functional noise tool IBM EinsCheck — Transistor-level electrical checking tool GateMaker — Transistor-level test model generation tool CPAM Common power analysis methodology Power, voltage drop, voltage rail electromigration checker IBM ChipBench — Chip viewing tool IBM EinsTimer — Chip timing tool 3DNoise — Chip functional noise tool Global EinsCheck — Chip electrical checking tool TestBench — Chip testability tool ASF Austin linear simulator flow Chip voltage drop and voltage rail electromigration checker DRC Design rule checking Technology rule checking LVS Layout versus schematic Layout and schematic equivalence tool YLD Yield Yield checking tool Niagara — Shape environment Erie Efficient rapid integrated extraction Macro extraction tool NMC Niagara methodology checks Hierarchy checker IMC Integration methodology checks Hierarchy checker RVIA Redundant via generation Auto via insertion MASH Migration assist shape handling Layout shapes manipulator ABG Abstract generator Hierarchy contract management tool MPA Macro power grid abstract Macro power grid extractor 3DX 3D extraction Chip wire extractor A netlist describes connectivity in an electronic design. R. BERRIDGE ET AL. IBM J. RES. & DEV. VOL. 51 NO. 6 NOVEMBER 2007 688 The IBM LAVA (leakage avoidance and analysis) application was added to exploit additional device types [high-voltage threshold (VT) and low-VT] for both custom and standard cell designs. High-VT devices were substituted for regular-VT devices in very noncritical circuit paths in order to minimize leakage, whereas lowVT devices were incorporated into the design in highly critical circuit paths for increased performance gain while maintaining low leakage levels. The combination of the EinsTuner and the LAVA applications, coupled with parameterized common components, allowed designers to optimize their pre-